february 2010 ? 1993 fairchild semiconductor corporation www.fairchildsemi.com 74lvx3245 8-bit dual supply transl ating transceiver with 3-state outputs general description the lvx3245 is a dual-supply, 8-bit translating transceiver that is designed to interface between a 3v bus and a 5v bus in a mixed 3v/5v supply environment. the transmit/ receive (t/ r ) input determines the direction of data flow. transmit (active-high) enables data from a ports to b ports; receive (active-low) enables data from b ports to a ports. the output enable input, when high, disables both a and b ports by placing them in a high impedance condition. the a port interfaces with the 3v bus; the b port interfaces with the 5v bus. the lvx3245 is suitable for mixed voltage applications such as notebook computers using 3.3v cpu and 5v peripheral components. features bidirectional interface between 3v and 5v buses inputs compatible with ttl level 3v data flow at a port and 5v data flow at b port outputs source/sink 24 ma guaranteed simultaneous switching noise level and dynamic threshold performance implements proprietary emi reduction circuitry functionally compatible with the 74 series 245 ordering code: order number package number package description 74lvx3245wm m24b 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74lvx3245qsc mqa24 24-lead quarter size outline package (qsop), jedec mo-137, 0.150" wide 74lvx3245mtc mtc24 24-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide devices also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. logic symbol/s pin descriptions pin names description oe output enable input t/ r transmit/receive input a 0 ?a 7 side a inputs or 3-state outputs b 0 ?b 7 side b inputs or 3-state outputs connection diagram/s
www.fairchildsemi.com 2 truth table/s inputs outputs oe t/ r l l bus b data to bus a l h bus a data to bus b h x high-z state h = high voltage level l = low voltage level x = immaterial logic diagram/s
3 www.fairchildsemi.com absolute maximum ratings (note 1) supply voltage (v cca , v ccb ) ? 0.5v to + 7.0v dc input voltage (v i ) @ oe , t/ r ? 0.5v to v cca + 0.5v dc input/output voltage (v i/o ) @ a n ? 0.5v to v cca + 0.5v @ b n ? 0.5v to v ccb + 0.5v dc input diode current (i in ) @ oe , t/ r 20 ma dc output diode current (i ok ) 50 ma dc output source or sink current (i o ) 50 ma dc v cc or ground current per output pin (i cc or i gnd ) 50 ma and max current @ i cca 100 ma @ i ccb 200 ma storage temperature range (t stg ) ? 65 c to + 150 c dc latch-up source or sink current 300 ma maximum junction temperature under bias (t j ) +150c recommended operating conditions (note 2) supply voltage v cca 2.7v to 3.6v v ccb 4.5v to 5.5v input voltage (v i ) @ oe , t/ r 0v to v cca input/output voltage (v i/o ) @ a n 0v to v cca @ b n 0v to v ccb free air operating temperature (t a ) ? 40 c to + 85 c minimum input edge rate ( t/ v) 8 ns/v v in from 30% to 70% of v cc v cc @ 3.0v, 4.5v, 5.5v note 1: the ?absolute maximum ratings? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ?recommended operating conditions ? table will define the conditions for actual device operation. note 2: unused pins (inputs and i/os) must be held high or low. they may not float. dc electrical characteristics symbol parameter v cca v ccb t a = + 25 c t a = ? 40 c to + 85 c units conditions (v) (v) typ guaranteed limits v iha minimum high level a n , t/ r , 3.6 5.0 2.0 2.0 v input voltage oe 2.7 5.0 2.0 2.0 v out 0.1v or v ihb b n 3.3 4.5 2.0 2.0 v cc ? 0.1v 3.3 5.5 2.0 2.0 v ila maximum low level a n , t/ r , 3.6 5.0 0.8 0.8 v input voltage oe 2.7 5.0 0.8 0.8 v out 0.1v or v ilb b n 3.3 4.5 0.8 0.8 v cc ? 0.1v 3.3 5.5 0.8 0.8 v oha minimum high level 3.0 4.5 2.99 2.9 2.9 v i out = ? 100 a output voltage 3.0 4.5 2.65 2.35 2.25 i oh = ? 24 ma 2.7 4.5 2.5 2.3 2.2 i oh = ? 12 ma 2.7 4.5 2.3 2.1 2.0 i oh = ? 24 ma v ohb 3.0 4.5 4.5 4.4 4.4 v i out = ? 100 a 3.0 4.5 4.25 3.86 3.76 i oh = ? 24 ma v ola maximum low level 3.0 4.5 0.002 0.1 0.1 v i out = 100 a output voltage 3.0 4.5 0.21 0.36 0.44 i ol = 24 ma 2.7 4.5 0.11 0.36 0.44 i ol = 12 ma 2.7 4.5 0.22 0.42 0.5 i ol = 24 ma v olb 3.0 4.5 0.002 0.1 0.1 v i out = 100 a 3.0 4.5 0.18 0.36 0.44 i ol = 24 ma i in maximum input leakage current 3.6 5.5 0.1 1.0 a v i = v ccb , gnd @ oe , t/ r i oza maximum 3-state v i = v il , v ih output leakage 3.6 5.5 0.5 5.0 a oe = v cca @ a n v o = v cca , gnd i ozb maximum 3-state v i = v il , v ih output leakage 3.6 5.5 0.5 5.0 a oe = v cca @ b n v o = v ccb , gnd
www.fairchildsemi.com 4 note 3: worst case package. note 4: max number of outputs defined as (n). data inputs are driven 0v to v cc level; one output at gnd. note 5: max number of data inputs (n) switching. (n ? 1) inputs switching 0v to v cc level. input-under-test switching: v cc level to threshold (v ihd ), 0v to threshold (v ild ), f = 1 mhz. ac electrical characteristics symbol parameters t a = + 25 c t a = ? 40 c to + 85 c t a = ? 40 c to + 85 c units c l = 50 pf c l = 50 pf c l = 50 pf v cca = 3.3v (note 6) v cca = 3.3v (note 6) v cca = 2.7v v ccb = 5.0v (note 7) v ccb = 5.0v (note 7) v ccb = 5.0v (note 7) min typ max min max min max t phl propagation delay 1.0 5.4 8.0 1.0 8.5 1.0 9.0 ns t plh a to b 1.0 5.6 7.5 1.0 8.0 1.0 8.5 t phl propagation delay 1.0 5.1 7.5 1.0 8.0 1.0 8.5 ns t plh b to a 1.0 5.7 7.5 1.0 8.0 1.0 8.5 t pzl output enable 1.0 4.8 8.0 1.0 8.5 1.0 9.0 ns t pzh time oe to b 1.0 6.3 8.5 1.0 9.0 1.0 9.5 t pzl output enable 1.0 6.3 8.5 1.0 9.0 1.0 9.5 ns t pzh time oe to a 1.0 6.8 9.0 1.0 9.5 1.0 10.0 t phz output disable 1.0 5.3 7.5 1.0 8.0 1.0 8.5 ns t plz time oe to b 1.0 4.2 7.0 1.0 7.5 1.0 8.0 t phz output disable 1.0 5.3 8.0 1.0 8.5 1.0 9.0 ns t plz time oe to a 1.0 3.7 6.5 1.0 7.0 1.0 7.5 t oshl output to output t oslh skew (note 8) 1.0 1.5 1.5 1.5 ns data to output note 6: voltage range 3.3v is 3.3v 0.3v. note 7: voltage range 5.0v is 5.0v 0.5v. note 8: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). parameter guaranteed by design. i cc maximum b n 3.6 5.5 1.0 1.35 1.5 ma v i = v ccb ? 2.1v i cct /input @ a n , t/ r , 3.6 5.5 0.35 0.5 ma v i = v cca ? 0.6v oe i cca quiescent v cca a n = v cca or gnd supply current 3.6 5.5 5 50 a b n = v ccb or gnd, oe = gnd, t/ r = gnd i ccb quiescent v ccb a n = v cca or gnd supply current 3.6 5.5 8 80 a b n = v ccb or gnd, oe = gnd, t/ r = v cca v olpa quiet output maximum 3.3 5.0 0.8 v (note 3) (note 4) v olpb dynamic v ol 3.3 5.0 1.5 v olva quiet output minimum 3.3 5.0 ? 0.8 v (note 3) (note 4) v olvb dynamic v ol 3.3 5.0 ? 1.2 v ihda minimum high level 3.3 5.0 2.0 v (note 3) (note 5) v ihdb dynamic input voltage 3.3 5.0 2.0 v ilda maximum low level 3.3 5.0 0.8 v (note 3) (note 5) v ildb dynamic input voltage 3.3 5.0 0.8 symbol parameter v cca v ccb t a = + 25 ct a = ? 40 c to + 85 c units conditions (v) (v) typ guaranteed limits
5 www.fairchildsemi.com capacitance symbol parameter typ units conditions c in input capacitance 4.5 pf v cc = open c i/o input/output 15 pf v cca = 3.3v capacitance v ccb = 5.0v c pd power dissipation a b 55 pf v ccb = 5.0v capacitance (note 9) b a 40 v cca = 3.3v note 9: c pd is measured at 10 mhz 8-bit dual supply translating transceiver the lvx3245 is a dual supply device capable of bidirec - tional signal translation. this level shifting ability provides an efficient interface between low voltage cpu local bus with memory and a standard bus defined by 5v i/o levels. the device control inputs can be controlled by either the low voltage cpu and core logic or a bus arbitrator with 5v i/o levels. manufactured on a sub-micron cmos process, the lvx3245 is ideal for mixed voltage applications such as notebook computers using 3.3v cpu's and 5v peripheral devices. power up considerations to insure that the system does not experience unneces - sary i cc current draw, bus contention, or oscillations during power up, the following guidelines should be adhered to (refer to ta b l e 1 ): ? power up the control side of the device first. this is the v cca . ? oe should ramp with or ahead of v cca . this will help guard against bus contention. ? the transmit/receive control pin (t/ r ) should ramp with v cca , this will ensure that the a port data pins are con - figured as inputs. with v cca receiving power first, the a i/o port should be configured as inputs to help guard against bus contention and oscillations. ? a side data inputs should be driven to a valid logic level. this will prevent excessive current draw. the above steps will ensure that no bus contention or oscil - lations, and therefore no excessive current draw occurs during the power up cycling of these devices . these steps will help prevent possible damage to the translator devices and potential damage to other system components. table 1. low voltage translator power up sequencing table device type v cca v ccb t/ r oe a side i/o b side i/o floatable pin allowed 74lvx3245 3v 5v ramp ramp logic outputs no (power up 1st) configurable with v cca with v cca 0v or v cca please reference application note an-5001 for more deta iled information on using fairchild?s lvx low voltage dual supply cmos translating transceivers.
www.fairchildsemi.com 6 physical dimensions 2.65 max 0.200.10 0.10 c c 15.400.20 a see detail a 0.33 0.20 notes: unless otherwise specified a) this package conforms to jedec ms-013, issue e, dated sept 2005. b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpatern standard: soic127p1030x265-24l pin one indicator 10.325 24 13 13.970 7.500.10 b x 45 0.75 0.25 (r0.10) (r0.10) 0.40~1.27 8 0 seating plane (1.40) 0.25 gage plane detail a scale: 2:1 seating plane 112 0.25 0.51 0.35 b ca m 1.27 land pattern recommendation 14.52 1.27 typ 0.55 typ 1.75 typ 9.2 10.95 e) drawing filename: mkt-m24brev2 24-lead small outline integrated circ uit (soic), jedec ms-013, 0.300" wide package drawings are provided as a service to custom ers considering fairchild components. drawings may change in any manner without notice. please note the re vision and/or date on the drawing and contact a fair- child semiconductor representative to verify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packag ing area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
.635 d. dimensions are exclusive of burrs, mold flash, and tie bar extrusions c. drawing conforms to asme y14.5m-1994 b. all dimensions are in millimeters a. this package conforms to jedec m0-137 variation ae notes : side view top view seating plane gage plane detail a end view land pattern recommendation 1 1 12 13 24 24 13 12 3.99 3.84 6 2x 12 tips 0.635 1.49 1.39 1.73 max 0.10 a-b 0.10 a-b 0.20 c 0.161 0.061 a b 0.178 c a-b d 24x 0.3 0.2 0.203 0.101 e. land pattern standard: sop63p600x175-24m f. drawing file name: mkt-mqa24rev2 5.60 1.75 0.4 8.74 8.59 0.71 0.61 45 8 2 0.61 0.71 r0.008 0 min 0.254 (0.695) 7 www.fairchildsemi.com 24-lead quarter size outline packag e (qsop), jedec mo-137, 0.150" wide package drawings are provided as a service to customers consideri ng fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and con- tact a fairchild semiconductor representative to verify or obtain the most recent revision. package specifi- cations do not expand the terms of fair child?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
date 10/97. mtc24rev4 1 12 b 24 13 a detail 12 t op & bottom 0.75 0.45 8 0- 1 12 13 24 r0.09min (1.00) 0.65 typ 0.20 cba 0.10 c b z 0.10 c 7.80.1 0.20 typ (4.45) (7.35) (1.45) 6.4 3.2 4.40.1 a 5.9 0.65 www.fairchildsemi.com 8 24-lead thin shrink small outline pa ckage (tssop), jedec mo-153, 4.4mm wide package drawings are provided as a service to custom ers considering fairchild components. drawings may change in any manner without notice. please note the re vision and/or date on the drawing and contact a fair- child semiconductor representative to verify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packag ing area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
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